The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has increased the complexity of IC processing and manufacturing.
For these advances of the IC processing and manufacturing to be realized, similar developments in IC packaging is also needed. For example, IC chips comprise semiconductor devices formed on a substrate such as a semiconductor wafer and include metalized contact, or attachment, pads for providing an electrical interface to the integrated circuitry. Conventional techniques for providing a connection between the internal circuitry of a chip and external circuitry, such as a circuit board, another chip, or a wafer, include wire bonding, in which wires are used to connect the chip contact pads to the external circuitry. A more recent chip connection technique, known as flip chip package, provides for coupling an IC chip to external circuitry using solder bumps that have been deposited onto the contact pads of the IC chip. In order to mount the chip to external circuitry (e.g., a substrate), the chip is flipped over in an upside-down manner and its contact pads are aligned with matching contact pads on the substrate. Underfill (an adhesive flowed between the chip and the substrate) is then flowed between the flipped chip and the substrate supporting the external circuitry to complete a mechanical and/or electrical interconnection between the IC device and the external circuitry. The resulting flip chip package is much smaller than a traditional carrier-based system, because the chip is positioned directly on the external circuitry, such that the interconnect wires may be much shorter. As a result, the inductance and resistive heat are greatly reduced, enabling higher-speed devices
However, due to the inherent coefficient of thermal expansion mismatches between components of the flip chip package such as for example the IC chip, the substrate, and the underfill, high package warpage and thermal stresses are frequently induced in the flip chip package. Such high thermal stresses and warpage not only lead to the delamination in the low-k interconnect layer(s) in the chip, but also cause solder bump cracks leading to failure, degrading the long term operating reliability of the flip chip package.